1. Field of the Invention
The present invention relates to semiconductor memory device operation, and more particularly, to a flash memory device and a method of erasing a flash memory device.
2. Description of the Related Art
Semiconductor memory devices are typically classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. The volatile semiconductor memory devices have fast reading and writing speeds, but their stored contents disappear when no external power is applied. In comparison, the non-volatile semiconductor memory devices retain stored contents even when no power is applied. Therefore, the non-volatile semiconductor memory devices are used to store contents, which must remain regardless of power supply. Examples of the non-volatile semiconductor memory devices are a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM).
Generally, since erase and write operations are relatively difficult in MROMs, PROMs and EPROMs, common users may not be able to update memory contents. To the contrary, since erase and write operations can be electrically performed in EEPROMs, they have become widely used in system programming and auxiliary memory devices, which require continuous updating. A flash EEPROM, in particular, has a higher degree of integration, as compared to a typical EEPROM. The flash EEPROM can therefore be particularly useful in a high-capacity auxiliary memory device. Among the types of flash EEPROMs, a NAND-type flash EEPROM (hereinafter, referred to as a NAND flash memory) has a higher degree of integration, as compared to other types of flash EEPROMs. In contrast, a NOR-type flash EEPROM (hereinafter, referred to as a NOR flash memory) has a relatively low degree of integration, but is capable of performing fast read and write operations.
A cell array of a NOR flash memory device is divided into memory regions (e.g., banks and blocks). Program and erase operations of the NOR flash memory device are performed according to these memory regions. During an erase operation, for example, a flash memory device is generally erased by blocks. In the NOR flash memory device, in particular, an erase voltage of 6 to 10 V is applied to a bulk of the block and a predetermined negative voltage of −10 V is applied to a word line for erasing. A bit line and a common source line of a memory cell maintain a floating state, and electrons implanted on a floating gate are removed by Fowler-Nordheim (F-N) tunneling when satisfying the above bias conditions.
An erase operation is especially important in the NOR flash memory device. Over-erased cells may reduce the reliability of a read operation in adjacent memory cells. Moreover, over-erased cells may cause program failure by interrupting a smooth program operation of adjacent memory cells when a series of program operations are performed after an erase operation. Thus, an over-erased memory cell may cause an error during a read operation and/or interrupt a program operation an adjacent memory cell.
FIG. 1 is a graphical view of threshold voltage distributions of over-erased cells in a typical NOR flash memory device. Referring to FIG. 1, threshold voltages of erased memory cells correspond to the voltage distribution 10. Ideal threshold voltage distributions of erased memory cells exist between a threshold voltage V1b and a threshold voltage V2, i.e., distribution 11. Memory cells having threshold voltage distributions between a threshold voltage V1a and a threshold voltage V1b, i.e., distribution 12 (indicated by hatching), are over-erased cells. Memory cells having threshold voltages in a threshold voltage distribution 20 are programmed cells. Although threshold voltage distributions of the programmed memory cells correspond to distribution 20, the programmed memory cells may be included in one of multiple threshold voltage distributions whenever memory cells store multi-bit data.
FIG. 2 is a circuit diagram showing limitations due to over-erased memory cells. Referring to FIG. 2, memory cells MC<0> to MC<4>are connected to the same bit line BL. It is assumed that the memory cells MC<0> to MC<4> are connected to the same common source line CSL, as well. In FIG. 2, the memory cells MC<0>, MC<1>, MC<3> and MC<4> are over-erased memory cells (indicated by hatching). The memory cell MC<2>is programmed with another threshold voltage state which is not an erase state. During a read operation, the memory cell MC<2> is selected such that a read voltage (approximately 4.5 V) is applied to the word line Sel WL of the selected memory cell MC<2>. A voltage of 0 V is applied to the unselected word lines Unsel WLs of the remaining memory cells MC<0>, MC<1>, MC<3> and MC<4>, which are not simultaneously selected.
At this point, a sense amplifier 30 senses a current flowing in the selected memory cell MC<2> in order to detect programmed data. However, when over-erased memory cells are intensively distributed in a specific region, the sense amplifier 30 may detect the selected memory cell MC<2> as an ON cell even though the selected memory cell MC<2> is actually an OFF cell. That is, since the over-erased memory cells MC<0>, MC<1>, MC<3> and MC<4> are OFF cells, the common source line CSL and the bit line BL must be cut off. However, the over-erased memory cells MC<0>, MC<1>, MC<3> and MC<4> cause leakage currents I1<0>, I1<1>, I1<3> and I1<4>, respectively, in a word line voltage of 0 V. The leakage currents I1<0>, I1<1>, I1<3> and I1<4> are provided from the bit line BL to sense the selected memory cell MC<2>. Accordingly, the sense amplifier 30 may sense the selected cell MC<2> as an ON cell due to the leakage currents I1<0>, I1<1>, I1<3> and I1<4>, even though the selected cell MC<2> is an OFF cell. This malfunction more often occurs in a specific cell array where over-erased cells are intensively distributed.
Various attempts to address the above described limitations caused by over-erased memory cells in a flash memory device are disclosed, for example, in U.S. Pat. No. 6,493,266, titled “SOFT PROGRAM AND SOFT PROGRAM VERIFY OF THE CORE CELLS IN FLASH MEMORY ARRAY,” U.S. Pat. No. 6,967,873, titled “MEMORY DEVICE AND METHOD USING POSITIVE GATE STRESS TO RECOVER OVER-ERASED CELL,” and U.S. Pat. No. 6,452,837, titled “NONVOLATILE SEMICONDUCTOR MEMORY AND THRESHOLD VOLTAGE CONTROL METHOD THEREFOR,” the contents of which are hereby incorporated by reference.
However, the above U.S. patents do not address an increase of a threshold voltage occurring during a post program operation. Accordingly, conventional flash memory devices are not capable of preventing an increased threshold voltage, which occurs during a post program operation.